This invention relates to a exposure mask pattern correction method and system for use in a lithography step included in a semiconductor manufacturing process.
In accordance with the development of semiconductor devices, demands for high integration are becoming stronger year by year. A buried channel MOS transistor as shown in FIG. 1 is generally known as an example of a high-speed transistor.
In the buried channel MOS transistor, a shallow n-channel layer 4, which has a conductivity type opposite to a semiconductor substrate 2, is formed in a surface portion of the substrate by, for example, ion implantation as shown in FIG. 1. Simply forming the n-channel layer, however, results in a depletion type MOS transistor. To avoid this, channel cutting is generally performed using, for example, a work function difference, thereby forming an enhancement type buried channel MOS transistor.
To make an enhancement type transistor, a method for changing the gate material in accordance with the kind of the transistor is often employed. For example, in the case of an n-channel element, a p.sup.+ -type polysilicon gate electrode 8 is provided on the element with a gate insulating film 6 interposed therebetween, while in the case of a p-channel element, an n.sup.+ -type polysilicon gate electrode is provided in a similar manner.
In the above-described MOS transistor, the channel for conducting a current is formed in a surface portion of the semiconductor as shown in FIG. 2. Accordingly, electrons in the channel will not be influenced by the crystal truncation rod scattering which may occur on the surface of the semiconductor, and can move at a movement speed close to that in the case of a bulk of electrons. Further, since a depletion layer is formed at a surface of the n-type layer on the drain side, the capacity between the gate and the drain is small, which means that the speed and current driving capacity of the element can be enhanced.
Moreover, since no pn-junction exists between the channel region and each of the source/drain regions, avalanche breakdown will not easily occur, and characteristic variations due to hot carrier implantation, which may be considered a serious problem in short-channel MOS devices, can be minimized.
As described above, where a buried channel transistor with various advantages is applied to both the n-channel and p-channel transistors formed in a single device, a p.sup.+ -type polysilicon gate electrode and an n.sup.+ -type polysilicon gate electrode are generally used for an n-channel element and a p-channel element, respectively.
Referring then to FIGS. 3A-3C, a case where two gate materials are simultaneously etched after lithography will be examined. As is shown in FIG. 3A, a gate oxide film 14 is formed on a substrate 12, and then a p.sup.+ -type polysilicon layer 16a and an n.sup.+ -type polysilicon layer 16b are formed on the film 14 in an n-channel region I and a p-channel region II, respectively.
After the underlayers are formed for gates as above, resist patterns 18a and 18b are formed on the p.sup.+ -type polysilicon layer 16a and the n.sup.+ -type polysilicon layer 16b, respectively, as shown in FIG. 3B. After that, gate etching and resist separating steps are executed, thereby obtaining gate materials as shown in FIG. 3C.
Although the two gate materials are both polysilicon, they contain different impurities of different concentrations. Accordingly, the gate materials may have different post-etching properties (i.e. they have different post-etching shapes, and different rates of dimensional change between before and after etching).
FIGS. 4A-4E are views, showing cases where different etching steps are performed so as to impart the same post-etching properties to both the gate materials.
First, a gate underlayer is formed in each of channel regions I and II as shown in FIG. 4A, and then resist layers 20a and 20b are provided on p.sup.+ -type and n.sup.+ -type polysilicon layers 16a and 16b, respectively, thereby forming an n-channel transistor gate pattern, as is shown in FIG. 4B.
Subsequently, gate etching and resist separation of the n-channel transistor are performed as shown in FIG. 4C, and then the resultant structure is coated with resist layers 22a and 22b, thereby forming a p-channel transistor gate pattern, as is shown in FIG. 4D. After that, gate etching of the p-channel transistor and then resist separation are performed, thereby forming two gate materials as shown in FIG. 4E.
Even if etching is performed individually in each of two channels as above, it is difficult to make the aforementioned post-etching properties completely identical. Moreover, in light of reduction of the number of processes, the FIGS. 3A-3C process is used more often than the FIGS. 4A-4E process.
In addition, the problem of an OPE (Optical Proximity Effect) is getting a great deal of attention in accordance with the development of semiconductor device refining techniques. The OPE will be described below.
In the manufacture of semiconductor devices, process conditions are adjusted so as to make the dimension of a portion of a minimum process margin in a designed circuit identical to a desired (designed) value. In general, that portion indicates a portion of a minimum design dimension. In the case of a semiconductor memory element, for example, a memory cell section of a highest pattern density corresponds to it.
If the process conditions are adjusted to the memory cell section as a high integration pattern, a peripheral circuit section as a comparatively low integration pattern cannot always have designed dimensions because of the effect of the process. This effect is called the optical proximity effect (OPE), which results from complicated combination of the influences of an optical image obtained after light transmission through an exposure mask, a latent image in a resist, the resist coating/developing process, the conditions of the underlayers, the manner of etching of the underlayers, a post process such as cleaning, oxidation, etc., an exposure mask process, etc.
The optical proximity effect does not always result from an optical factor. To solve the OPE problem, OPC (Optical Proximity Correction) research on correcting designed dimensions when forming masks is being carried out in lots of institutes these days. From, for example, academic society theses, most present OPC techniques relate to correction using optical image simulation.
However, as aforementioned, the OPE is caused by a mask/wafer forming process, as well as an optical factor. Therefore, to realize highly accurate correction, it is necessary to inspect the OPE on a wafer obtained through the actual total process, and to perform dimension correction when forming a mask.
The Bucket method (L. Liebman et al. SPIE Vol. 2322 Photomask Technology and Management (1994) 299), for example, is known as a one-dimensional gate pattern correction method which considers the total process. In this method, the relationship (dependency upon pattern density) of a finished dimension bias (the difference between the actual finished dimension and a desired one) as shown, for example, in FIG. 5A, to a distance between a target pattern and a pattern adjacent thereto is obtained using a TEG (Test Element Group) for finished dimension measurement called "an ACLV (across the chip linewidth variation)" and formed of a wafer manufactured through the total process. Thereafter, the designed circuit is corrected by a finished dimension bias resulting from the dependency of a pattern dimension variation upon the pattern density, which is obtained by electrical measurements as shown in FIG. 5B. A correction table as shown in FIG. 7 is created on the basis of data shown in FIG. 5B, and used to correct an actual circuit pattern.
Specifically, after a to-be-corrected region is extracted, the width of a space between each pair of all adjacent patterns is calculated. If, for example, adjacent patterns GC are arranged as shown in FIG. 6, spaces of widths a, b, c, d and e are defined between the patterns GC.
Concerning the adjacent space widths a-e, a correction table shown in FIG. 7 is referred to. It is determined which space width on the correction table corresponds to each of the adjacent space widths a-e, and then a corresponding pattern is corrected using a correction amount based on the determined width.
However, since in the conventional OPC techniques, a correction amount is determined only for the distance to the adjacent pattern, they cannot realize highly accurate OPC for different gate materials where a single device includes transistors which contain the different gate materials (the above-described conventional case uses a p.sup.+ -type polysilicon gate and an n.sup.+ -type polysilicon gate).
Moreover, to realize, from now on, accurate correction in a device with a single gate pattern formed of a plurality of gate materials, a mask pattern correction method is necessary for individually correcting those portions of the mask pattern which are formed of different gate materials.